1. Field of the Invention
The present invention relates to an emitter coupled logic (ECL) apparatus, and more particularly, to an active pull down (APD) type ECL apparatus.
2. Description of the Related Art
A prior art ECL apparatus includes a current switch formed by an input transistor and a reference transistor, and an emitter follower as an output circuit controlled by a collector voltage of the input transistor. Particularly, when the ECL apparatus is connected to a large connection load capacity, an active pull down circuit is provided and connected to the emitter follower, thereby rapidly and surely changing an output voltage from high to low (see: JP-A-HEI3-106222). In this case, the active pull down circuit is connected to a collector of the reference transistor. This will be explained later in detail.
In the above-mentioned APD type ECL apparatus, however, since a discharging current flowing to the collector of the reference transistor from the active pull down circuit does not sufficiently contribute to the switching of the current switch, the speed of the output voltage from low to high is not rapid.
In order to enhance the speed of the output voltage from low to high, an APD type ECL apparatus, a so-called super push-pull logic (SPL) apparatus, has been known. This will be also explained later in detail.
In the above-mentioned SPL apparatus, however, since a non-threshold logic circuit is provided instead of the current switch, the operation is unstable.